Unit NANOMETER CMOS IC DESIGN
- Course
- Electronic engineering for the internet-of-things
- Study-unit Code
- 70A00107
- Curriculum
- Elettronica per l'internet of things
- Teacher
- Daniele Passeri
- Teachers
-
- Daniele Passeri
- Hours
- 76 ore - Daniele Passeri
- CFU
- 9
- Course Regulation
- Coorte 2017
- Offered
- 2018/19
- Learning activities
- Caratterizzante
- Area
- Ingegneria elettronica
- Academic discipline
- ING-INF/01
- Type of study-unit
- Obbligatorio (Required)
- Type of learning activities
- Attività formativa monodisciplinare
- Language of instruction
- Italian
- Contents
- I. (1 CFU) Nanoelectronics Devices and Technologies.
II. (2 CFU) CMOS static and dynamic IC logic design.
III. (4 CFU) CMOS VLSI design of a digital system.
IV. (2 CFU) VLSI CAD Laboratory. - Reference texts
- J. Rabaey, A. Chandrakasan and B. Nikolic, "Digital Integrated Circuits: A Design Perspective", 2/e, Prentice Hall 2003.
Harry Veendrick, “Nanometer CMOS ICs: from Basics to ASICs”, ed. Springer. - Educational objectives
- At the end of the course, students are provided with methodologies and tools for the design of integrated circuits / systems on a nanometer scale. Ability to justify design choices at different abstraction levels of integrated circuits and systems. Using of advanced VLSI CAD tools (layout editor, automatic placement & routing, synthesis).
- Prerequisites
- In order to understand and know how to apply the content and methodologies of teaching it is advisable to cover the concepts of basic analogue and digital electronics (in particular, the operation of the MOSFET transistor) and the basic concepts of Boolean algebra.
- Teaching methods
- Lectures, classroom exercises, computer exercises, classroom and laboratory experiments.
- Other information
- None.
- Learning verification modality
- Realization of two projects (mid-term and final) and oral examination, mandatory.In particular, the topics of the projects will be- mid-term: process and device simulation of a Tunnel FET (TFET).- final: report on a CAD VLSI project of a typically numerical integrated circuit / system (e.g. adders, multipliers)The oral examination is aimed at verifying the student's skills and application of methodologies and tools for the design of nanoscale circuits / systems, the ability to justify design choices in view of the state of the art of IC’s technology.
- Extended program
- I. (1 CFU) Nanoelectronics Devices and Technologies. State-of-the-art Technology CAD design tools: process and device simulation for new material/device optimization. Innovative nano-electronics devices for autonomous sensor network design: ISFET, BioFET, Tunnel FET devices.II. (2 CFU) CMOS static and dynamic IC logic design. Static CMOS logic family: Combinational circuits: dynamic logic Pre-charge/Evaluation (P/E), Domino. Sequential circuits: clocked CMOS logic (C2MOS), NORA, TSPCL.
III. (4 CFU) CMOS VLSI design of a digital system. High-level logic synthesis. Introduction to hardware description languages: VHDL. Datapath. Arithmetic units: adders with different carry propagation routing strategies. Ripple Carry Adder (RCA), Carry Propagate Adder (CPA), Carry Skip Adder, Manchester Carry Chain, Carry Look-Ahead, Brent-Kung. Serial and Parallel Multipliers: Carry Save Multiplier. Dividers. Memories. Organization and synthesis of control units. Low-power VLSI design solution: time-based design for future sensor interfaces (highly digital approach, area efficiency driven scaling, ultra-low voltage capability, energy efficiency)
IV. (2 CFU) VLSI CAD Laboratory. Introduction to VLSI computer aided design: the major CAD tools in the analysis and synthesis of integrated circuits: layout editor, DRC tools, Placement and Routing. ELECTRIC VLSI Design System, SIS. VLSI CAD Lab exercises: front-to-back design case studies.