Unit COMPUTER ARCHITECTURE
- Course
- Informatics
- Study-unit Code
- 20009205
- Curriculum
- In all curricula
- Teacher
- Alfredo Navarra
- Teachers
-
- Alfredo Navarra
- Raffaella Gentilini (Codocenza)
- Hours
- 42 ore - Alfredo Navarra
- 21 ore (Codocenza) - Raffaella Gentilini
- CFU
- 9
- Course Regulation
- Coorte 2021
- Offered
- 2021/22
- Learning activities
- Base
- Area
- Formazione informatica di base
- Academic discipline
- INF/01
- Type of study-unit
- Obbligatorio (Required)
- Type of learning activities
- Attività formativa monodisciplinare
- Language of instruction
- Italian
- Contents
- MODULE I: This module provides a primer in digital logic design, focusing on (1) boolean functions and boolean algebra (2) combinational circuit analysis and synthesis (3) basics of sequential circuits.
MODULE II:
Numbers representation: positional, sign-and-magnitude, twos' complement; Designs of adders, multipliers, and dividers; Floating points: 16 bit standard IEEE 754; Cellular automata: Game of Life, Scintillae and Computer architecture; Abstraction levels: Functional level, RTL. Micro-oprerations. Control Unit. Machine cycle. PDP8: register level, functional level, control unit, Assembly. Cache memory. Pipelining. - Reference texts
- MODULE I:
1. Cristiana Bolchini, Carlo Brandolese, Fabio Salice, Donatella Sciuto. Reti Logiche. Maggioli Editore, 2015, Apogeo Education.
MODULE II:
2. F. Barsi: Architettura degli elaboratori, parte seconda: struttura dei sistemi. Margiacchi-Galeno
3. C. Hamacher, Z. Vranesic, S. Zaky, Naraig Manjikian: Introduzione all'architettura dei calcolatori III edizione. McGraw-Hill - Educational objectives
- Knowledge and understanding about basic properties of a computer, including assembly programming
- Prerequisites
- none
- Teaching methods
- Face-to-face
Practical training
Seminars - Learning verification modality
- examination in class
- Extended program
- MODULE I: Boolean algebra and logic gates: basic theorems and properties of boolean algebra, boolean functions, canonical forms, digital logic gates. Gate level minimization (Karnaugh method and Quine McCluskey method). Combinational Logic: combination circuits, analysis and design procedure, special circuits (Ripple-Carry Adder, Decoders, Encoders, Multiplexers). Synchronous sequential circuits (basics): storage element (Latches,Flip-Flops), Mealy and Moore machines.
MODULE II: Numbers representation: positional, sign-and-magnitude, twos' complement; Designs of adders and multipliers; Floating points: 16 bit standard IEEE 754; Computer architecture abstraction levels: Functional level, RTL. Micro-oprerations. Control Unit. Machine cycle. PDP8: register level, functional level, control unit, Assembly. Cache memory. Pipelining